Test MP+dmb.sy+[fr-rf]-addr-rfi-addr-ctrlisb

AArch64 MP+dmb.sy+[fr-rf]-addr-rfi-addr-ctrlisb
"DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Rfi DpAddrdR DpCtrlIsbdR Fre"
Cycle=Rfi DpAddrdR DpCtrlIsbdR Fre DMB.SYdWW Rfe FrLeave RfBack DpAddrdW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdW DpAddrdR DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpAddrdW Rfi DpAddrdR DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X9=a; 1:X11=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | MOV W4,#1           |             ;
 STR W2,[X3] | STR W4,[X5,W3,SXTW] |             ;
             | LDR W6,[X5]         |             ;
             | EOR W7,W6,W6        |             ;
             | LDR W8,[X9,W7,SXTW] |             ;
             | CBNZ W8,LC00        |             ;
             | LC00:               |             ;
             | ISB                 |             ;
             | LDR W10,[X11]       |             ;
Observed
    z=1; y=2; x=1; 1:X6=1; 1:X2=0; 1:X10=1; 1:X0=2;
and z=1; y=1; x=1; 1:X6=1; 1:X2=0; 1:X10=1; 1:X0=2;
and z=1; y=2; x=1; 1:X6=1; 1:X2=0; 1:X10=1; 1:X0=1;
and z=1; y=1; x=1; 1:X6=1; 1:X2=0; 1:X10=1; 1:X0=1;